Conventionally, for a pixel structure and an operation of a MOS-type image sensor used in a solid-state imaging device, proposed has been a method in which pixels of the MOS-type image sensor are controlled in rows, by sharing a common drain between a reset transistor and an amplify transistor, both of which are included in each pixel (see patent document 1). Hereinafter, a conventional solid-state imaging device disclosed in patent document 1 will be described with reference to FIG. 6 and FIG. 7.
FIG. 6 is a diagram describing a detailed circuit structure of a pixel section used in the conventional solid-state imaging device disclosed in patent document 1.
A pixel A comprises a photodiode 111a, a transfer transistor 112a, a reset transistor 113a, and an amplify transistor 114a. A pixel B comprises a photodiode 111b, a transfer transistor 112b, a reset transistor 113b, and an amplify transistor 114b. Each of the photodiodes 111a and 111b generates signal electric charges. To gates of the transfer transistors 112a and 112b, transfer control signals Ta and Tb are supplied, respectively, and the transfer transistors 112a and 112b transfer (read) the signal electric charges generated in the photodiodes 111a and 111b to the signal accumulation sections 102a and 102b in accordance with the transfer control signals Ta and Tb, respectively. To gates of the reset transistors 113a and 113b, reset control signals Ra and Rb are supplied, respectively, and the reset transistors 113a and 113b reset the signal electric charges accumulated in the signal accumulation sections 102a and 102b in accordance with the reset control signals Ra and Rb, respectively. The amplify transistors 114a and 114b amplify the signal electric charges accumulated in the signal accumulation sections 102a and 102b, respectively, so as to be outputted to a common output signal line 115. A constant current source 116 is connected to the output signal line 115. Furthermore, a pixel selection signal SEL supplied to a drain of each of the amplify transistors 114a and 114b outputs a power source voltage level or a ground level.
FIG. 7 is a timing chart describing an operation of the conventional solid-state imaging device. At a timing of time t0 shown in FIG. 7, all levels of the pixel selection signal SEL, the reset control signals Ra and Rb, the transfer control signals Ta and Tb are ground levels, and both of the pixels A and B are unselected.
At a timing of time t1, the level of the pixel selection signal SEL becomes a power source voltage level. And, a level of the output signal line 115 becomes the power source voltage level. Next, at a timing of time t2, the level of the reset control signal Ra becomes the power source voltage level. Accordingly, the reset transistor 113a is turned on. At this timing, the pixel A is selected. Then, at a timing of time t3, the level of the reset control signal Ra becomes the ground level. Accordingly, the reset transistor 113a is turned off. A period from the time t3 to the time t4 is a period of reading a reset level of the pixel A.
Next, at a timing of time t4, the level of the transfer control signal Ta becomes the power source voltage level. Accordingly, the transfer transistor 112a is turned on. Then, at a timing of time t5, the level of the transfer control signal Ta becomes the ground level. Accordingly, the transfer transistor 112a is turned off. During a period from the time t4 to the time t5, the electric charges are transferred from the photodiode 111a to the signal accumulation section 102a, thereby causing a potential level of the signal accumulation section 102a to decrease from a potential level of the pixel selection signal SEL by a potential level of the photodiode 111a. Accordingly, the electric charges fluctuated as described above are outputted to the output signal line 115 via the amplify transistor 114a. As a result, a level of the electric charges fluctuated as described above is read as a level of a pixel signal of the pixel A. A period from the time t5 to the time t6 is a period of reading the pixel signal of the pixel A.
Next, at a timing of time t6, the level of the pixel selection signal SEL becomes the ground level. Accordingly, both the pixels A and B become unselected again. Thereafter, at a timing of time t7, the level of the pixel selection signal SEL becomes the power source voltage level. And, the level of the output signal line 115 becomes the power source voltage level. Next, at a timing of time t8, the level of the reset control signal Rb becomes the power source voltage level. Accordingly, the reset transistor 113b is turned on. At this timing, the pixel B is selected. Next, at a timing of time t9, the level of the reset control signal Rb becomes the ground level. Accordingly, the reset transistor 113b is turned off. A period from the time t9 to the time t10 is a period of reading a reset level of the pixel B.
Next, at a timing of time t10, the level of the transfer control signal Tb becomes the power source voltage level. Accordingly, the transfer transistor 112b is turned on. Then, at a timing of time t11, the level of the transfer control signal Tb becomes the ground level. Accordingly, the transfer transistor 112b is turned off. During a period from the time t11 to the time t12, the electric charges are transferred from the photodiode 111b to the signal accumulation section 102b, thereby causing a potential level of the signal accumulation section 102b to decrease from the potential level of the pixel selection signal SEL by a potential level of the photodiode 111b. Accordingly, the electric charges fluctuated as described above are outputted to the output signal line 115 via the amplify transistor 114b. As a result, a level of the electric charges fluctuated as described above is read as a level of a pixel signal of the pixel B. A period from the time t11 to the time t12 is a period of reading the pixel signal of the pixel B.
As described above, the conventional solid-state imaging device can execute read operations of selecting pixels, resetting the pixels, and transferring electric charges from photodiodes. Furthermore, such read operations can be executed in rows.    [Patent document 1] Japanese Laid-Open Patent Publication No. 2005-5911